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Tsung-Yi Wu Tel:04-7232105 Ext 7297 |
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索引: |
Professional biography |
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Tsung-Yi Wu received the Ph.D.
degree in computer science from the National Tsing-Hua University, Taiwan, in
1997. From 1997 to 2001, he was with Taiwan Semiconductor Manufacturing
Company (TSMC), responsible for developing advanced design automation technologies.
In 2004, he joined the Department of Electronic Engineering at National
Changhua University of Education, Taiwan, where he is currently an assistant
professor. |
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研究專長與興趣
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台積電主任工程師 (Principal Engineer, TSMC)、科雅科技經理 (Manager, Goyatek) |
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Ａ、 期刊論文 （ Refereed Papers ） 1.
Tsung-Yi Wu, Tzi-Wei Kao, How-Rern Lin “Combined Use
of Rising and Falling Edge Triggered Clocks for Peak Current Reduction in
IP-Based SoC/NoC Designs,” IEICE Transactions on Fundamentals of Electronics,
Communications and Computer Sciences, vol. E93-A, no. 12, pp. 2581-2589,
2010. (SCI) (NSC 98-2221-E-018 -015 -) Ｂ、 研討會論文 （ Conference Papers ） 1.
Tsung-Yi Wu, Shi-Yi Huang et al., "A High Speed Design Using
Divide-and-Conquer Architecture for Motion Estimation", IEEE
Symposium on Low-Power and High-Speed Chips, 2011. C、專利 1. 中華民國發明專利：內嵌式記憶體讀取時間之量測系統與方法。專利號碼:
00540057。專利權法定起迄日: 2. 美國發明專利：System and measuring access time of embedded memories。專利號碼：6424583。專利權法定起日: 3. 美國發明專利：Logic Circuit。專利號碼：US
7,795,923 B1。專利權法定起日: |
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歷年碩士畢業論文
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