Tsung-Yi Wu
吳宗益 教授
Professor
Dept. of Electronic Engineering,
National Changhua University of Education,
1, Jin-De Rd., Changhua City, Taiwan 500

Tel:04-7232105 Ext 7297
Fax:04-7211078
Email: tywu@cc.ncue.edu.tw

索引:

Professional biography
Education

Research Interests
Experiences
Research Grants
Publications
MS student(s)

 

Professional biography sketch

Tsung-Yi Wu received the Ph.D. degree in computer science from the National Tsing-Hua University, Taiwan, in 1997. From 1997 to 2001, he was with Taiwan Semiconductor Manufacturing Company (TSMC), responsible for developing advanced design automation technologies. In 2004, he joined the Department of Electronic Engineering at National Changhua University of Education, Taiwan, where he is currently an assistant professor.

學歷 (Education)

  • 清華大學資科所博士 (Ph.D. Degree, Computer Science, National Tsing-Hua University)

研究專長與興趣

  • 設計自動化 (EDA), 超大型積體電路設計 (VLSI Circuit Design),多媒體  (Multimedia)

經歷 (Experiences)

台積電主任工程師 (Principal Engineer, TSMC)、科雅科技經理 (Manager, Goyatek)

研究計劃 (Research Grants)

計 畫 名 稱

計畫內擔任之工作

起迄年月

補助或委託機構

雙值邏輯+與傳統邏輯閘合成器之研究(II)

主持人

100/8~101/7

國科會

雙值邏輯+與傳統邏輯閘合成器之研究(I)

主持人

99/8~100/7

國科會

Publications

A、 期刊論文 Refereed Papers

1.         Tsung-Yi Wu, Tzi-Wei Kao, How-Rern Lin “Combined Use of Rising and Falling Edge Triggered Clocks for Peak Current Reduction in IP-Based SoC/NoC Designs,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E93-A, no. 12, pp. 2581-2589, 2010. (SCI) (NSC 98-2221-E-018 -015 -)

B、 研討會論文 Conference Papers

1.         Tsung-Yi Wu, Shi-Yi Huang et al., "A High Speed Design Using Divide-and-Conquer Architecture for Motion Estimation", IEEE Symposium on Low-Power and High-Speed Chips, 2011.

 

C、專利

1.     中華民國發明專利:內嵌式記憶體讀取時間之量測系統與方法專利號碼: 00540057專利權法定起迄日: 2003/07/01 - 2020/06/27。發明人: 宋乃胤,吳宗益等。

2.     美國發明專利:System and measuring access time of embedded memories專利號碼6424583。專利權法定起日: 2002/07/23。發明人: 宋乃胤,吳宗益。

3.     美國發明專利:Logic Circuit專利號碼US 7,795,923 B1。專利權法定起日: 2010/09/14。發明人︰吳宗益。

 

MS student(s)

  •  

歷年碩士畢業論文

入學年度

姓名

96

李泰輪

邏輯閘合成器

A Logic Fate Synthesizer